1. Field of the Invention
This invention relates to the field of integrated circuits in general, and to a method and circuit for detecting an overflow condition during multiplication of operands in particular.
2. Description of the Relevant Art
Microprocessors determine the speed and power of personal computers and a growing number of more powerful machines. Microprocessors handle most of the data processing in the machine in which they are installed. Microprocessors typically include at least three functional groups: the input output unit (I/O), the control unit, and the arithmetic logic unit (ALU). The I/O unit interfaces between external circuitry and the ALU and the control unit. I/O units frequently include signal buffers for increasing the current capacity of a signal before the signal is sent to external components. The control unit controls the operation of the microprocessor by fetching instructions from the I/O unit and translating the instructions into a form that can be understood by the ALU. In addition, the control unit keeps track of which step of a given program is being executed. The ALU handles the mathematical computations and logical operations that are performed by the microprocessor. The ALU executes the decoded instructions received from the control unit to modify data contained in registers within the microprocessor.
An essential component of an ALU is the multiplication circuit. The multiplication circuit typically performs multiplication operations on at least two input operands. Often times the multiplication of two operands will result in an overflow condition. Generally, overflow occurs when the result of the multiplication does not fit the representation being used.
Overflow in multiplication can occur in signed or unsigned operations. With respect to unsigned operations, overflow occurs when the product of two n bit operands exceeds n bits. Stated another way, if any of the n most significant bits of the 2n bit product result operand equals logical one, then an overflow condition occurs. With respect to signed operations, an overflow condition occurs if any of the n most significant bits of the 2n bit product result operand does not equal the n.sup.th least significant bit (e.g., the sign bit) of the result operand.
FIG. 1 shows a prior art overflow detection circuit 10 coupled to a multiplier circuit 12. Multiplier circuit 12 is configured to receive two n bit operands a.sub.n-1:0 and b.sub.n-1:0. Multiplier circuit 12 is configured to generate a result operand (r.sub.2n-1:0) up to two n bits in length as a function of the input operands a.sub.n-1:0 and b.sub.n-1:0. With respect to unsigned multiplication, overflow detection circuit analyzes the n most significant bits of r.sub.2n-1:n-1 to determine whether any is a logical one. With respect to signed operand multiplication, overflow detection circuit 10 checks the n+1 bits of r.sub.2n-1:n-1 to determine whether they are all equal. Overflow detection circuit 10 generates a signal indicating overflow if either of the two conditions arise.
Because multiplication and overflow detection is one of the most commonly invoked operations during the execution of the computer program, the speed with which the circuit shown in FIG. 1 operates is extremely important in determining the overall speed of the system. As can be seen in FIG. 1 multiplier circuit 12 and overflow detection circuit 10 operate sequentially. In other words, overflow detection circuit 10 does not operate to detect overflow until the n or n+1 (depending upon whether overflow is being checked in a signed or unsigned operation) most significant bits of result operand r.sub.2n-1:0 are available from multiplier circuit 12. The sequential nature of operation of the circuit shown in FIG. 1 adds delay to the overall operation of microprocessor employing the same. It would therefore be desirable to produce a multiplier circuit with overflow detection that achieves a significant reduction in time required to produce results.